1. Field of the Invention
The present invention relates to a data processor realizing a high processing capability by a parallel processing mechanism, and, more particularly, relates to a data processor capable of executing a plurality of instructions in parallel.
2. Description of the Related Art
In recent years, together with its high processing speed resulting from the improvement of operating frequency, a data processor is making a remarkable progress in performance due to the development of parallel processing techniques such as pipeline processing or superscalar techniques. A superscalar technique is a technique for decoding and executing a plurality of instructions in parallel. For example, Japanese Patent Application Laid-Open No. 3-91029 (1991), discusses a data processor which decodes and executes, in parallel, two instructions with no operand interference. The data processor uses a superscalar technique that cannot execute certain combinations of instructions in parallel such as instructions having an operand interference or instructions whose operand is a memory operand. A key to the improvement of performance is in increasing the combination of instructions capable of being executed in parallel.
In a conventional data processor, in most cases, two instructions whose operands are interdependent are not executed at the same time by simply connecting operators in series.
Known data processors execute two instructions having operand interference in parallel by serially connecting ALU's in two steps or by simply connecting operators in series. However, it is difficult to obtain a high speed operation and to improve the operating frequency of the data processor.
In order to execute, in parallel, two instructions having a memory operand or whose operand is a memory operand, it is necessary to execute two memory accesses in parallel. In order to access the two independent memory operands in parallel, it is necessary to provide two ports on a main memory or a cache memory, or to have an interleaved memory by providing multi-ports on only a tag memory of a built-in cache. In a conventional data processor having such a configuration, in order to execute in parallel the two instructions having two memory operands, a large amount of hardware must be added and the control becomes complicated.
In such a way, in order to improve the performance of the data processor by using a superscalar system, it is important to increase the combination of the instructions executable in parallel. However, as mentioned above, it is difficult to execute, in parallel, the two instructions having operand interference at high speed. Also, in order to execute two instructions accessing the memory in parallel, a large amount of hardware is required.